Senior ASIC Research Engineer - Front-end Digital Design

USC's Information Sciences Institute (ISI), a unit of the university's Viterbi School of Engineering, is a world leader in the research and development of advanced information processing, computing, communications and artificial intelligence technologies. ISI's 400 faculty, professional staff and graduate students carry out extraordinary information sciences research at three distinct locations - Arlington, VA; Marina Del Rey, CA; and Waltham, MA.

ISI's Computational Systems & Technology Division has an opening in Arlington, VA for a Senior ASIC Research Engineer - Front-end Digital Design, to design advanced ASIC prototypes addressing problems of national importance. The Engineer will work with a cutting-edge team to design and verify register-transfer level (RTL) models of CPUs, memories, and accelerators for applications such as communications, signal processing, and security. The Engineer will have opportunities to collaborate with ISI's MOSIS 2.0 service, integrate third-party IP cores, and gain experience working with top research sponsors such as DARPA, IARPA, and the CHIPS Act. The position provides a collaborative, flexible university setting with rich learning and growth opportunities. The Engineer will gain experience in a fast-moving research setting and work toward a better and more secure future.

The work will be based in ISI's Arlington, VA office.

• Ability to handle Controlled Unclassified Information (CUI). Per U.S. government regulations, eligibility to handle CUI requires U.S. Citizenship or Permanent Residency.
• Degree in Computer Engineering, Electrical Engineering, or related field
• Master's degree with >5 years of experience
• Demonstrated excellence creating digital designs with Verilog, System Verilog, or VHDL RTL
• Solid understanding of computer architecture and microarchitecture
• Demonstrated skills with EDA tools (logic synthesis, timing), scripting, revision control

• Familiarity with digital design verification
• Familiarity with performance modeling
• Familiarity with agile hardware design methodologies
• Experience with AI-assisted workflows
• Experience using FPGAs
• Effective at verbal communication and giving clear explanations

The annual base salary range for this position is $140,000 to $170,000. When extending an offer of employment, the University of Southern California considers factors such as (but not limited to) the scope and responsibilities of the position, the candidate's work experience, education/training, key skills, internal peer equity, federal, state, and local laws, contractual stipulations, grant funding, as well as external market and organizational considerations.

• Work on exciting and engaging projects that have real-life impact.
• Small project team environment allows for involvement across entire project lifecycle.
• A quality work-life balance.
• Opportunities for free, top-tier university education for you and your children.
• Great benefits - medical to matched retirement