Principal STA Engineer

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You are a seasoned engineering professional with a passion for tackling complex timing challenges in advanced-node System-on-Chip (SoC) development. With deep expertise in static timing analysis, sign-off methodologies, and constraints development, you thrive in environments where precision and collaboration are paramount. You possess a proven track record of successful tapeouts at cutting-edge nodes (7nm, 5nm, 3nm), and you are comfortable navigating the intricacies of variation-aware timing, crosstalk, and clock distribution. Your technical acumen extends to scripting and tool automation, enabling you to streamline analysis and reporting workflows for efficiency and accuracy.

As a Principal Engineer, you are not only a technical authority but also a mentor and leader. You proactively engage with cross-functional teams-RTL designers, physical design specialists, and SI/PI engineers-to drive timing convergence and ensure robust, reliable silicon. Your communication skills allow you to lead timing reviews and sign-off meetings with clarity and confidence, influencing architectural decisions and advocating for best practices. You are committed to continuous learning and innovation, eager to explore new methodologies and technologies that advance the state of the art in SoC timing closure. If you are ready to make a significant impact and shape the future of silicon design, Synopsys offers the platform and community to realize your ambitions.

• Owning full-chip and block-level STA sign-off across all PVT corners and operational modes.
• Driving timing closure from synthesis through place-and-route to tapeout, ensuring first-pass silicon success.
• Analyzing and resolving setup/hold violations, noise, signal integrity (SI), OCV, and derates.
• Defining and validating timing margins, guard-bands, and sign-off criteria for advanced node designs.
• Managing complexities at 7nm, 5nm, and 3nm nodes, including variation-aware timing (AOCV/POCV), crosstalk, and clock distribution.
• Developing and reviewing SDC constraints (clocks, IO delays, exceptions) for MCMM designs.
• Building scalable timing methodologies and driving constraint validation and consistency across teams.
• Utilizing STA tools (Primetime, Tempus) and scripting (Tcl/Python) for automation and flow efficiency.
• Leading timing reviews and sign-off meetings with cross-functional stakeholders.

• Ensuring successful tapeouts and robust silicon performance at advanced technology nodes.
• Driving innovation in timing sign-off methodologies, influencing industry standards and best practices.
• Reducing time-to-market by achieving efficient timing closure and minimizing design iterations.
• Enhancing cross-functional collaboration and knowledge sharing within Synopsys engineering teams.
• Mentoring and developing junior engineers, building a stronger and more resilient team.
• Contributing to architectural decisions that improve timing convergence and silicon reliability.
• Streamlining timing analysis workflows through automation, improving productivity and accuracy.

• B.Eng,or MS in Electrical Engineering or a related field.
• 10-15+ years of experience in STA and timing sign-off for SoCs.
• Proven record of successful tapeouts in advanced nodes (7nm, 5nm, 3nm).
• Expertise in STA tools (Primetime, Tempus) and scripting languages (Tcl, Python, Perl).
• Deep understanding of EM/IR and reliability impacts on timing.
• Experience with full-chip integration and hierarchical STA methodologies.
• Ability to develop scalable timing methodologies for MCMM designs.

• Technical leader and mentor, passionate about knowledge sharing.
• Collaborative communicator, able to lead cross-functional teams and drive consensus.
• Detail-oriented and analytical, with a relentless focus on quality and accuracy.
• Innovative thinker, eager to explore new approaches and technologies.
• Adaptable, capable of navigating fast-paced and evolving engineering environments.
• Confident decision-maker, able to advocate for best practices and influence architectural choices.

You will join a dynamic, highly skilled SOC engineering team dedicated to delivering world-class silicon solutions at the forefront of semiconductor technology. The team is composed of experts in physical design, RTL architecture, SI/PI analysis, and verification, working collaboratively to achieve first-pass silicon success. You'll have opportunities to lead, mentor, and collaborate with some of the brightest minds in the industry, all committed to innovation and excellence.

We are open to candidates based in Austin, Phoenix, Dallas and Sunnyvale

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.