ASIC Design Verification Engineer - Risc V and/or Systolic Array experience required

Category:

Engineering

Employment Type:

Contract

Reference:

BH-392411

ASIC Design Verification Engineer - Risc V and/or Systolic Array experience required

As a Senior ASIC Design Verification Engineer, you will be responsible for verifying critical blocks in an inference chiplet that enable efficient execution of AI models ranging from small to large scale. Your primary focus will be on systolic array-based compute architectures, ensuring correctness, performance, and scalability across hierarchical designs.

Key Responsibilities:

• Lead comprehensive verification planning and execution for systolic array compute blocks and full-chip designs, ensuring robust validation across all design hierarchies.
• Collaborate cross-functionally with architecture, firmware, and design teams to develop detailed test plans that validate systolic dataflow, compute behavior, and control logic
  against specifications and requirements.
• Design and implement advanced testbenches featuring constrained-random stimulus generation, intelligent checkers, comprehensive scoreboards, and targeted assertions to ensure correctness of array-level computation, data movement, and synchronization.
• Architect and execute verification strategies encompassing test planning, coverage analysis, automated regression management, and data-driven insights to maximize verification efficiency and quality for high-throughput compute architectures.
• Drive verification excellence through established methodologies including structured code reviews, agile sprint planning, and systematic feature deployment processes.
• Innovate verification approaches by researching and implementing next-generation methodologies, automated flows, and emerging technologies, including AI-driven verification tools
  and performance-aware validation techniques.

• Proven Experience:
  7-10+ years of hands-on verification experience spanning test plan development, simulation environment creation, test implementation, and complex debugging across diverse IP blocks, SoCs, and system-level designs.
• Specialized Expertise:
  Demonstrated proficiency in systolic array or accelerator-class compute block verification, including validation of dataflow, pipeline behavior, and scalability at array and chip levels.
• Technical Mastery:
  Advanced skills in SystemVerilog/Verilog, UVM methodology, and C/C++ programming, including embedded code development and validation for RISC V-based or accelerator control processors.
• Verification Leadership:
  Established track record in creating scalable verification flows, implementing coverage-driven verification strategies, and developing assertion-based verification frameworks for compute-intensive architectures.

• Medical, Prescription, Dental & Vision Benefits (for employees working 20+ hours per week)
• Health Savings Account (HSA) (for employees working 20+ hours per week)
• Life & Disability Insurance (for employees working 20+ hours per week)
• MetLife Voluntary Benefits
• Employee Assistance Program (EAP)
• 401K Retirement Savings Plan
• Direct Deposit & weekly epayroll
• Referral Bonus Programs
• Certification and training opportunities