Senior Technical Leader, EPYC SOC Architecture

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THE ROLE:

As part of the EPYC Datacenter SOC team, you will be responsible for customer and business engagement on technical capabilities and deployment in the EPYC roadmap. This position leverages a strong technical background and deep knowledge of the design of EPYC processors and platforms to deliver differentiated customer and business value for a growing EPYC portfolio and product-line.

THE PERSON:

Has the ability to work with customers and business stakeholders to understand their key care abouts, and most importantly, a deep technical knowledge of modern datacenter CPU deployments. You need to be willing to dive deeply into the capabilities and engineering of EPYC CPUs to provide real, implementable, and appropriate analysis to appropriately motivate incorporation of new capabilities or optimization of existing capabilities. Those same attributes will also be utilized to appropriately scrutinize and reject ideas which aren't implementable, have poor deployment possibilities, or are lacking appropriate return-on-roadmap investment. You will also be responsible for working with design teams on specifications, design, and otherwise to ensure realization of new capabilities.

KEY RESPONSIBILITIES:

As part of this work, horizontal organizational integration and leadership will be a key job function. This means developing a deep technical understanding of existing AMD designs, ability to form and document detailed execution plans and specifications, collaboration with presilicon and post-silicon execution, verification, validation, and firmware teams, etc. Further, as a key contributor to definition of advanced technologies, ability to span not just technical, but also customer and business relationship understanding are required skills. You will have either demonstrated strong breadth, or, a few depth areas and a track record for eagerly and quickly learning new areas and skills. To accommodate global customer interactions, a moderate amount of travel as-well-as work-hour flexibility to accommodate multiple time zones will be required.

PREFERRED EXPERIENCE:

• Memory Technologies: DDR, LPDDR, and emerging multi-tier memory systems (hardware design, hardware-software co-design, ecosystem enablement, customer and business collaboration)
• On-chip coherence protocol, external IO subsystems, caching, and scalability optimizations working with Performance, IO, and Infinity Fabric Design teams for Datacenter CPU designs
• Pathfinding and alignment between Datacenter CPU and Datacenter HPC/Training/Inference product lines including unique attributes of AI-Head-Node CPU deployments and capabilities
• Advanced chiplet attach architecture including 3^rd party chiplet integration strategy
• Development of virtualization and QoS architectures, including security and related attributes
• SOC-level and platform power delivery requirements and management architecture including feature definition and detailed operational attributes
• Product and Platform cost optimization for improving TCO of EPYC solutions
• Customer view of Total Cost of Ownership (TCO) optimization and key aspects which can be influenced by the design of EPYC CPU and Platform solutions
• Proven ability to create compelling internal and external presentations for maximizing customer and business interaction; ability to meet the audience where they are in level of understanding, interest, and focus to facilitate compelling solutions to business and customer needs

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